1. Field of the Invention
The present invention relates generally to clock synthesis, and more particularly, to a clock synthesizer that synthesizes a clock signal from a parallel data stream using a serializer.
2. Description of the Related Art
Most electronic systems employ a clock signal to control and synchronize the timing of operations that are carried out by them. In a system for testing electronic devices, multiple clocks are employed in various applications and each clock is selected, configured or designed based on its particular application. The main system clock, for example, is required to be extremely accurate. On the other hand, the clock that is used by analog modules of the test apparatus has the following requirements:                Low jitter (less than 2 picoseconds RMS);        Tunable to a very fine resolution in frequency;        Be able to skew to an external trigger with no glitches; and        Be able to hop to different frequencies with minimal delays.        
Conventional clock designs have been inadequate in providing the requirements for the analog clock set forth above. Clocks that have the ability to provide low jitter and high accuracy, e.g., the type of clocks that are used as the main system clock, are typically unable to hop to different frequencies with minimal delays. Also, it is difficult to skew or align the phase of such clocks to an external signal, e.g., a trigger. Some conventional clocks allow for dynamic frequency changes, but they are not desirable because they introduce delays that are too long when hopping from one frequency to another.
Cost is often an additional requirement for analog clocks used in a test system, because they are installed in multiple devices, e.g., in each test instrument of the test system that contains an analog module. When low cost is added as a requirement in the design of an analog clock, it becomes even more evident that conventional clock designs are inadequate.